The present invention relates to a power-up detection scheme in an integrated circuit. More specifically, the present invention relates to a circuit for detecting when the VDD (core) voltage reaches the correct level for operating an associated circuit.
FIG. 1 is a circuit diagram of a conventional VDD power-up detection circuit 100 and an associated circuit 111, which is powered by a VDD supply voltage. VDD power-up detection circuit 100 includes n-channel MOS transistors 101-103, p-channel MOS transistor 104 and Schmidt trigger circuit 110. N-channel transistor 101 is a conventional thin oxide transistor of the type typically used in circuit 111. N-channel transistor 103 is a thick oxide transistor, which has a gate oxide that is thicker than that of n-channel transistor 101. N-channel transistor 101 has a threshold voltage of about 370 milli-Volts (mV). Thick oxide transistor 103 has a threshold voltage of about 430 mV. N-channel transistor 102 is a low-threshold voltage transistor (as indicated by the triangle in the channel region of this transistor), which has a threshold voltage of about 240 mV. An additional implant mask is required to form low-threshold voltage transistor 102.
N-channel transistors 101 and 102 are connected in series between the VDD voltage supply terminal and the ground voltage supply terminal. More specifically, n-channel transistor 101 is coupled between the VDD voltage supply terminal and node N01, and n-channel transistor 102 is coupled between node N01 and the ground voltage supply terminal. The gates of n-channel transistors 101 and 102 are commonly connected to the VDD voltage supply terminal.
P-channel transistor 104 and n-channel transistor 103 are connected in series between the VDD voltage supply terminal and the ground supply terminal. More specifically, p-channel transistor 104 is coupled between the VDD voltage supply terminal and node N02, and n-channel transistor 103 is coupled between node N02 and the ground voltage supply terminal. The gate of p-channel transistor 104 is coupled to the ground voltage supply terminal, and the gate of n-channel transistor 103 is coupled to node N01. Node N02 is coupled to provide a voltage V02 to Schmidt trigger circuit 110.
During power-up, the voltage on the VDD voltage supply terminal increases from a value of 0 Volts to the nominal VDD supply voltage. N-channel transistors 101-103 and p-channel transistor 104 are initially turned off when the VDD supply voltage is equal to 0 Volts. When the VDD supply voltage starts to increase, p-channel transistor 104, which has a gate coupled to ground, ideally turns on first with the desired behavior of subthreshold conduction. Thus, the output voltage V02 on node N02 initially tracks the increasing VDD supply voltage.
As the VDD supply voltage increases, the low-threshold voltage n-channel transistor 102 will turn on faster than n-channel transistor 101. As a result, the low-threshold voltage n-channel transistor 102 initially pulls down the voltage on node N01, thereby ensuring that n-channel transistor 103 remains off, and the output voltage V02 on node N02 continues to track the VDD supply voltage. In order for this to occur, the subthreshold conduction of transistor 101 must be less than the threshold conduction of transistor 102.
As the VDD supply voltage continues to increase, n-channel transistor 101 turns on stronger, thereby causing the voltage on node N01 to be pulled up. Eventually, the voltage on node N01 becomes high enough to turn on n-channel transistor 103. At this time, the voltage V02 on node N02 begins to be pulled down toward ground. Schmidt trigger circuit 110 detects when this voltage V02 drops below the VDD supply voltage by a predetermined percentage. Upon detecting this voltage drop, trigger circuit 110 asserts a logic high enable signal EN111, which is used to activate circuit 111. It is intended that circuit 111 is only enabled after the VDD supply voltage has reached an acceptable level for operating this circuit 111.
However, in order for circuit 100 to operate as described above, the following conditions must be met by transistors 101-104. First, the subthreshold conductance of low threshold voltage transistor 102 must be greater than the subthreshold conductance of transistor 101, in order to ensure that node N01 is not pulled up to the VDD supply voltage when the VDD supply voltage is less than the threshold voltage of low threshold voltage transistor 102 (240 mV). Second, the subthreshold conductance of transistor 101 must be less than the on-conductance of low threshold voltage transistor 102, thereby ensuring that node N01 is pulled down when the VDD supply voltage is greater than the threshold voltage of transistor 102 (240 mV), but less than the threshold voltage of transistor 101 (370 mV). Third, as the VDD supply voltage increases, the on-conductance of transistor 101 must become greater than the on-conductance of low threshold transistor 102, thereby ensuring that node N01 is eventually pulled up toward the VDD supply voltage. Fourth, the on-conductance of p-channel transistor 104 must be greater than the subthreshold conductance of n-channel transistor 103, thereby ensuring that the voltage V02 tracks the VDD supply voltage while the voltage on node N01 is less than the threshold voltage of n-channel transistor 103 (430 mV). Finally, as the VDD supply voltage increases, the on-conductance of n-channel transistor 103 must become greater than the on-conductance of p-channel transistor 104, thereby ensuring that node N02 is eventually pulled down toward the ground supply voltage.
If the above-listed relationships are not true, circuit 100 may operate improperly. For example, if the subthreshold conductance of transistor 101 is greater than the on-conductance of low-threshold voltage transistor 102, then the voltage on node N01 may be pulled up toward the VDD supply voltage, thereby causing the voltage on node N02 to be pulled low relative to the VDD supply voltage. In this case, Schmidt trigger circuit 110 may erroneously activate the enable signal EN111, before the VDD supply voltage has reached an acceptably high voltage. The same result may occur if the subthreshold conductance of transistor 101 is greater than the subthreshold conductance of transistor 102, or if the subthreshold conductance of transistor 103 is greater than the on-conductance of p-channel transistor 104.
Conversely, if the on-conductance of transistor 102 is greater than the on-conductance of transistor 101, then the voltage on node N01 may be pulled down toward the ground supply terminal, such that transistor 103 fails to turn on. In this case, the voltage V02 will continue to be pulled up to the VDD supply voltage, and Schmidt trigger circuit 101 will not activate the enable signal EN111, even after the VDD supply voltage has reached an acceptable operating level. The same result may occur if the on-conductance of transistor 104 is greater than the on-conductance of transistor 103.
As VDD supply voltages become smaller, approaching levels of 1.2 Volts and lower, the sub-threshold currents become larger, such that the above listed requirements cannot be reliably met. Moreover as the VDD supply voltage decreases, it becomes difficult to significantly increase the on-conductance of transistor 101 relative to the on-conductance of transistor 102 (i.e., the width of transistor 101 must become unrealistically large). In reality, it is difficult, if not impossible, to design transistors 101 and 102 such that transistor 101 is able to reliably overpower transistor 102 before the VDD supply voltage exceeds 700 mV.
It would therefore be desirable to have a circuit that is capable of reliably detecting when a VDD supply voltage having a relatively low nominal voltage (e.g., 1.2 Volts or less) reaches an acceptable level during power-up. It would also be desirable if such a circuit does not require low threshold voltage transistors, thereby eliminating an additional implant mask.
Accordingly, the present invention provides a VDD power-up detection circuit that includes a p-channel transistor having a source coupled to a VDD voltage supply terminal, a drain coupled to a first node, and a gate coupled to a ground supply terminal. A first resistor (or a diode element) is coupled between the first node and the ground supply terminal. An n-channel transistor has a source coupled to the ground supply terminal, a drain coupled to a second node, and a gate coupled to the first node. A second resistor is coupled between the second node and the VDD voltage supply terminal. A trigger circuit is coupled to receive a control voltage from the second node.
Initially, the p-channel transistor is turned off because the VDD supply voltage is less than the threshold voltage of the p-channel transistor. The p-channel transistor is designed such that the subthreshold conductance of the p-channel transistor is less than the conductance of the first resistor. As a result, the control voltage on the first node is initially pulled down to the ground supply voltage through the first resistor.
At this time, the low voltage on the first node turns off the n-channel transistor. The n-channel transistor is designed such that the subthreshold conductance of the n-channel transistor is less than the conductance of the second resistor. As a result, the control voltage on the second node is initially pulled up to the VDD supply voltage through the second resistor.
The first and second resistors ensure well-behaved and predictable signal characteristics when the VDD supply voltage is less than the threshold voltages of the p-channel transistor and the n-channel transistor. Advantageously, there is no need to depend on the relative subthreshold conductances of different transistors. As a result, the VDD power-up detection circuit of the present invention will not prematurely indicate that the VDD supply voltage has reached an acceptable level. This predictability is desirable in a critical circuit such as a VDD power-up detect circuit.
As the VDD supply voltage increases during power-up, the p-channel transistor begins to turn on, thereby pulling up the voltage on the first node. The p-channel transistor is designed such that the on-conductance of the p-channel transistor becomes greater than the conductance of the first resistor, when the VDD supply voltage reaches a predetermined voltage greater than the threshold voltage of the p-channel transistor, but less than the full VDD supply voltage.
As the voltage on the first node increases, the n-channel transistor begins to turn on, thereby pulling down the control voltage on the second node. The n-channel transistor is designed such that the on-conductance of the n-channel transistor becomes greater than the conductance of the second resistor when the voltage on the first node reaches a predetermined voltage greater than the threshold voltage of the n-channel transistor, but less than the full VDD supply voltage.
When the control voltage on the second node is pulled down below a predetermined percentage of the VDD supply voltage, the trigger circuit activates an enable signal, which is used to enable an associated circuit to operate from the VDD supply voltage.
Advantageously, the trigger circuit does not activate the enable signal until after the VDD supply voltage has exceeded at least the threshold voltages of both the p-channel transistor and the n-channel transistor. This ensures that the VDD supply voltage has reached an appropriate level before the associated circuit, which likely includes both n-channel and p-channel transistors, is enabled to operate from the VDD supply voltage.
The VDD power-up detect circuit of the present invention advantageously requires fewer active circuit elements than conventional VDD power-up detection circuit 100, thereby providing for a smaller layout area. The VDD power-up detection circuit of the present invention also advantageously requires fewer types of circuit elements than conventional VDD power up detection circuit 100, thereby reducing the circuit variables. Moreover, because the VDD power-up detection circuit of the present invention does not require low threshold voltage transistors, an additional implant mask is not required.
The present invention will be more fully understood in view of the following description and drawings.